The capability to test digital logic inside Integrated Circuits (ICs) is a chief concern of electronic system vendors. Many different forms of circuits are used for products, by commercial and industrial customers, including Integrated Circuits (ICs), electronic circuits, semiconductors, Very Large Scale Integrated Circuits (VLSICs), Application Specific Integrated Circuits (ASICs), circuitry on printed circuit boards (PCBs), nanotechnology circuits, and other types of circuits. With increasing functionality, circuitry is growing more dense and more complex, and testing is becoming an exponentially more difficult task. Scan is a method commonly used for testing circuitry. Types of scan include, but are not limited to, Boundary Scan, Joint Test Action Group (JTAG), or other methods. Using scan, a user has direct access to testing flip-flops (also known as “flip flops” or “flops”), thereby bypassing datapath logic that is used in normal operation.
For a multi-gigahertz processor, speed improvement that saves just half of a gate delay may result in a product frequency speedup of 8 to 10 percent. It would be helpful that such a speed improvement also result in the same, or improved, scan functionality.